Selecting a Reduced but Representative Workload

Simulating a new microprocessor system is extremely timeconsuming due to the large number of dynamic instruction counts that need to be simulated. In the computer architecture community, there are two methods available to address this issue, sampling and reduced inputs. This paper presents a methodology that is based on statistical data analysis techniques which allows us to determine whether trace sampling is to be prefered over reduced inputs. As such, a reduced but representative workload is composed. We believe this methodology is also useful in other areas such as middleware benchmarking.